Wafer-level Spatial and Flush Delay Analysis for IDDQ Estimation

Rising levels and spread in IDDQ values render single threshold IDDQ testing obsolete for high- performance chips for deep sub-micron technologies. Increased inter-die and intra-die variations cause unacceptable yield loss with a single pass/fail limit. Use of spatial information to estimate fault-free IDDQ is investigated. Flush delay information is used to refine this estimate under varying process conditions. The analysis of SEMATECH test data is presented.