Modular, Fabric-Specific Synthesis For Programmable Architectures

Lecture Notes in Computer Science(2002)

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摘要
Traditionally, programmable fabrics consist of look up table (LUT) based programmable logic blocks (PLBs). Typically, the PLBs are either homogeneous (consisting of LUTs of the same size), or heterogeneous (consisting of LUTs of varying sizes). To bridge the cost-performance gap between ASICs and FPGAs, several new programmable logic fabrics are employing highly heterogeneous PLB architectures, consisting of a combination of LUTs of varying sizes, MUXes, logic gates, and versatile local routing architectures. Currently, there axe two possible approaches to Synthesis for such fabrics. In the generic Synthesis approach, the first step of technology mapping generates a netlist of functions that can be implemented by individual logic elements of a PLB, like LUTs, MUXes and logic gates. The second step of packing clusters these functions into groups of logic that can fit in a single PLB. The second approach constructs a library of certain PLB configurations (like a standard cell library) and performs library based technology mapping, followed by packing. In this paper, we show that both these approaches result in sub-optimal and uneven fabric utilization for two reasons: (a) a lack of fabric-specific knowledge; (b) a lack of integration between mapping and packing. We present a new, modular, Synthesis approach, consisting of a fabric-specific technology mapping algorithm which maps directly to the entire PLB, rather than individual logic elements. In this manner, the new approach integrates the steps of mapping and packing, resulting in higher fabric utilization. Using the highly heterogeneous eASIC PLB as an example, we demonstrate that our approach requires 22% and 24% fewer PLBs than the generic and library based Synthesis approaches, across a standard benchmark set. We also demonstrate the modularity of our approach, by comparing three PLB architectures. Our results show that highly heterogeneous PLBs are much more area efficient than homogeneous PLBs.
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关键词
individual logic element,logic gate,synthesis approach,technology mapping,varying size,PLB architecture,certain PLB configuration,entire PLB,heterogeneous PLB architecture,heterogeneous eASIC PLB,Fabric-Specific Synthesis,Programmable Architectures
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