Highly Manufacturable 32Mb ULP-SRAM Technology by Using Dual Gate Process for 1.5V Vcc Operation

D. H. Kim, S. J. Kim,B. J. Hwang,S. H. Seo,J. H. Choi,H. S. Lee,W. S. Yang,M. S. Kim,K. H. Kwak,J. Y. Lee,J. Y. Joo, J. H. Kim,K. Koh,S. H. Park,J. I. Hong

msra（2002）

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摘要

For 1.5V low Vcc operation and high performance full-CMOS low power SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology includes i)0.11um fine patterning implemented by phase shift mask(PSM) and optical proximity correction(OPC), ii)dual gate CMOS transistor with thin gate oxide, iii)improvement of Co salicide process to minimize the leakage current. These results enable to achieve 32Mb high density 6T LP SRAM cell.

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关键词

cmos memory circuits,sram chips,integrated circuit metallisation,leakage currents,low-power electronics,phase shifting masks,proximity effect (lithography),rapid thermal annealing,ultraviolet lithography,0.11 micron,1.5 v,1.5v vcc operation,32 mbit,co salicide technology,cosi,dual gate cmos transistor,dual gate process,fine patterning,full-cmos ultra low power sram,high density 6t ulp-sram cell,leakage current minimization,optical proximity correction,phase shift mask,thin gate oxide,ultra-shallow junction,leakage current,low power electronics,space technology,cmos technology,fabrication,threshold voltage

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