Optimizing effective interconnect capacitance for FPGA power reduction

    FPGA, 2014.

    Cited by: 9|Bibtex|Views16|Links
    EI
    Keywords:
    parasitic capacitance reductionfpga power reductionpower consumptioneffective parasitic capacitancetri-state routing bufferMore(12+)

    Abstract:

    We propose a technique to reduce the effective parasitic capacitance of interconnect routing conductors in a bid to simultaneously reduce power consumption and improve delay. The parasitic capacitance reduction is achieved by ensuring routing conductors adjacent to those used by timing critical or high activity nets are left floating - di...More

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