Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise.
2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS（2008）
Key words
Boolean algebra,automatic test pattern generation,flip-flops,integrated circuit noise,optimisation,CASTR,automatic test pattern generation,capture and shift toggle reduction,dynamic test compaction,flip-flop toggles,peak power supply noise,power reduction,pseudo Boolean optimization
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