A Novel Fpga Logic Block For Improved Arithmetic Performance
FPGA08: ACM/SIGDA International Symposium on Field Programmable Gate Arrays Monterey California USA February, 2008(2008)
摘要
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional fast carry-chains that concatenate adjacent compressors and can be routed locally without the global routing network. Unlike previous carry-chains for binary and ternary addition, the carry chain used by the new cell only spans 2 logic blocks, which significantly improves the delay of multi-input addition operations mapped onto the FPGA. The delay and area overhead that arises from augmenting a traditional FPGA logic cell with the new compressor structure is minimal. Using this new cell, we observed an average speedup in combinational delay of 1.41 x compared to adder trees synthesized using ternary adders.
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关键词
FPGA,Compressor Tree,6:2 Compressor,Multi-operand Addition,Carry-chain,Arithmetic Circuits
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