Process Variation Dimension Reduction Based On Svd

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV: DIGITAL SIGNAL PROCESSING-COMPUTER AIDED NETWORK DESIGN-ADVANCED TECHNOLOGY(2003)

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摘要
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and timing analysis under process variation can be performed efficiently. Our algorithm reduces the number of process variation variables while preserving the delay function with respect to process variation. Compared with the principal component analysis (PCA) method, our algorithm requires less computation time and guarantees the reduced process variation variables are independent. Experimental results on ISCAS85 circuits show that the algorithm works well.
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关键词
circuit simulation,fault simulation,integrated circuit modelling,singular value decomposition,SVD,circuit simulation,delay function preservation,fault simulation,process variation dimension reduction,process variation variable reduction,singular value decomposition,timing analysis,
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