Longest path selection for delay test under process variation

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2005, Pages 98-103.

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摘要

Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay among all paths through that fault site. There are often multiple longest paths for each fault site in the circuit, due to different process conditions. To detec...更多

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