Ibm System Z Functional And Performance Verification Using X-Gen

In the IBM System z10 (TM) project, new hardware components such as a processor core, memory and 10 subsystem as well as new packaging components have been designed. In this paper we describe how functional hardware verification has been applied to verify the correctness of system related functions. A huge challenge is to prove that the system performance with respect to bandwidth and latency actually matches the predictions as well as the actual prototypes. This paper describes a new method that has been introduced in order to verify the system performance using simulation of RTL models. The paper further describes the application of a model-based random test case generator named X-Gen to provide complex testing scenarios, intelligent background noise, and expected results. It concludes with the results of the verification approaches with respect to finding functional and performance related hardware inefficiencies during the design implementation phase.