A High-Speed And High-Precision Winner-Select-Output (Wso) Asic
1997 IEEE NUCLEAR SCIENCE SYMPOSIUM - CONFERENCE RECORD, VOLS 1 & 2（1998）
摘要
The design and performance characteristics of a 16-channel Winner-Select-output (WSO) ASIC are presented. The WSO ASIC does a fast comparison of 16 analog input voltages, outputs the maximum signal, the "second" maximum (partner) signal, and their addresses. The WSO ASIC chip is a key component of an analog electronics system being developed for a depth of interaction (DOI) PET detector module. The basic cell of the WSO ASIC is a "winner take all" (WTA) circuit. The precision of the WSO ASIC is enhanced by using a cascade structure WTA cell. The chip requires a single +5V supply and consumes 35 mW of power. The WSO ASIC is sensitive to voltage differences as small as 10 mV. The propagation delay of the chip is less than 30 nsec for voltage differences of >50 (typical for proposed application).
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关键词
scintillation counters,cascade structure wta cell,nuclear electronics,wso asic,analogue integrated circuits,cascade structure,16-channel wso asic,voltage differences,maximum signal,winner take all,analog electronics system,doi pet detector module,application specific integrated circuits,propagation delay,depth of interaction pet detector module,analog input voltages,high-speed and high-precision winner-select-output asic,detector circuits,positron emission tomography,winner take all circuit,wta circuit,second maximum partner signal,high-speed high-precision winner-select-output asic,performance characteristics,chip,face detection,cmos technology,detectors,photonic crystals,decoding,voltage
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