Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（2014）
摘要
In this paper, we demonstrate that standard cell design methodology can be applied to design vertical slit field effect transistor (VeSFET)-based ASICs with modern CMOS EDA tools. We study a family of VeSFET canvases—chain canvases that improve performance and power consumption of circuits mapped to them compared to circuits implemented with VeSFET canvases composed of isolated transistors. We compare the designs implemented with a commercial low power CMOS library and corresponding VeSFET libraries. VeSFET-based designs demonstrate significant power reduction as compared to the CMOS-based designs at the same performance.
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关键词
power consumption,twin-gate,cmos eda tools,vestics,standard cell design methodology,vesfet-based asics,cmos-based designs,regular layout,low power cmos library,cmos integrated circuits,application specific integrated circuits,eda infrastructure,vertical slit field effect transistor,field effect transistors,isolated transistors,integrated circuit design,low power,vesfet,low volume asics,low cost transistor,low energy,electronic design automation,power reduction,junctionless,cmos-oriented eda infrastructure,canvas,vesfet canvases
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