Post-silicon Tunable Clock Buffer Allocation Based on Fast Chip Yield Computation
Fifteenth International Symposium on Quality Electronic Design（2014）
关键词
Monte Carlo methods,buffer circuits,clocks,flip-flops,graph theory,Monte-Carlo simulation,clock delay,clock timing variation,control circuitry,design space exploration,flip-flops,graph-based chip yield computation technique,incremental PST buffer allocation,magnitude run time improvement,nontrivial implementation area,post-silicon tunable clock buffer allocation,process variation
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