Using many-core architectural templates for FPGA-based computing (abstract only).

Truly unleashing the computing potential of FPGAs, as well as widening their applicability, demands alleviating cumbersome HDL programming and relieving laborious manual optimization. Towards this end, we propose a Many-core Approach to Reconfigurable Computing (MARC) that enables efficient high-performance computing for applications expressed with imperative programming languages such as C/C++ without constructing FPGA computing machines from scratch when targeting various applications within the same or similar problem domains. A MARC system achieves high computing performance by leveraging a many-core architectural template, sophisticated logic synthesizing techniques, and state-of-art compiler optimization technology. In addition, MARC exploits abundant special FPGA resources such as distributed block memories and DSP blocks to implement complete single-chip high efficiency many-core microarchitectures. The key benefits of MARC include (i) allowing programmers to easily express parallelism through a high-level programming language, (ii) supporting coarse-grain multithreading and dataflow-style fine-grain threading while permitting bit-level resource control, and (iii) greatly reducing the effort required to re-purpose the hardware system for different algorithms or different applications.