A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract).David Jefferson,Srinivas Reddy,Christopher Lane, Ninh Ngo,Wanli Chang, Manuel Mijia,Ketan Zaveri,Cameron McClintock,Richard CliffFPGA(1998)引用 0|浏览32暂无评分AI 理解论文溯源树样例生成溯源树,研究论文发展脉络Chat Paper正在生成论文摘要