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We have proposed the use of 3D integration circuit technology to enhance the security of digital integrated circuits via circuit obfuscation

Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation

USENIX Security, pp.495-510, (2013)

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Abstract

The fabrication of digital Integrated Circuits (ICs) is increasingly outsourced. Given this trend, security is recognized as an important issue. The threat agent is an attacker at the IC foundry that has information about the circuit and inserts covert, malicious circuitry. The use of 3D IC technology has been suggested as a possible tech...More

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Introduction
  • The security of digital integrated circuits (ICs), the building blocks of modern computer hardware systems, can be compromised by covertly inserted malicious circuits.
  • The threat from such maliciously inserted hardware is of increasing concern to government and military agencies [2] and commercial semiconductor vendors.
  • This incident has further heightened the perceived threat from maliciously inserted hardware, and effective counter-measures to deter or prevent such attacks are of increasing importance
Highlights
  • The security of digital integrated circuits (ICs), the building blocks of modern computer hardware systems, can be compromised by covertly inserted malicious circuits
  • Wire lifting and placement/routing are performed using automated software tools, the former based on algorithms that we propose in this paper, and the latter using commercially available software from electronic design automation (EDA) vendors
  • We have proposed the use of 3D integration circuit technology to enhance the security of digital integrated circuits via circuit obfuscation
  • By implementing a subset of wires on the top tier, which is manufactured in a trusted fabrication facility, we obfuscate the identity of gates in the bottom tier, deterring malicious attackers
  • We propose practical approaches to determining the security level given a subset of lifted wires, and of identifying a subset of wires to lift to achieve a desired security level
  • We show, using a DES circuit case study, that 3D integrated circuits based circuit obfuscation can significantly reduce the ability of an attacker to carry out an effective attack
Results
  • The authors conduct the experimental study using two exemplar benchmarks, the c432 circuit from the ISCAS-85 benchmark suite [10] (a 27-channel bus interrupt controller) with ≈ 200 gates, and a larger DES encryption circuit with ≈ 35000 gates.
  • For 3D integration, bond points are assumed to be spaced at a pitch of 4μm, allowing for one bond-point per 16μm2.
  • This is consistent with the design rules specified in the Tezzaron 0.13μm technology kit.
  • Circuit synthesis was performed using the Berkeley SIS tool [27].
  • Placement and routing is performed using Cadence Encounter.
  • The authors used miniSAT as the SAT solver [29]
Conclusion
  • Three aspects of the attack and defense models deserve further mention. First, the authors note that the attack model described above subsumes a number of other practically feasible attack models.
  • Given the notion of k-security, a natural question to ask is whether there are stronger or different attack models for which k-security would be inadequate.
  • The authors discuss this in the context of two attack models that differ from the one assumed.
  • The authors show, using a DES circuit case study, that 3D IC based circuit obfuscation can significantly reduce the ability of an attacker to carry out an effective attack
Tables
  • Table1: Power, delay, wire length and area analysis for different levels of security on the c432 circuit. 1∗ is the base circuit with no wires lifted and 48∗ has all of the wires lifted
  • Table2: Technology libraries used for the experiment in
Download tables as Excel
Related work
  • HDL Code always @(posedge clk) for(i=0;i<33;i=i+1) key_c_r[i+1] <= #1 key_c_r[i]; Synthesis

    Technology Library Netlist

    Malicious Observer Wire Lifting Trusted Unlifted Netlist Lifted Wires Layout

    Placement and Routing Layout

    Fabrication Bottom Tier
  • In this section, we discuss related work in the literature on hardware security and, specifically, the use of 3D ICs in this context. We also discuss the relationship of our work to database and graph anonymizing mechanisms.

    Hardware Security Malicious circuits are expected to consist of two components, a trigger and the attack itself. The trigger for the attack can be based on data, for example when a specific cheat code appears at selected wires in the circuit [19], or on time, i.e., the trigger goes off after a certain period of time once the IC is shipped [33].

    Once triggered, the malicious attack can either transmit or leak sensitive information on the chip, modify the circuit functionality or degrade the circuit performance. Tehranipoor and Koushanfar discuss a number of specific backdoors that fall within one of these categories [31].
Funding
  • The work was supported by funding from the NSERC Discovery and Strategic grant programs. 508 22nd USENIX Security Symposium
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