Tree optimization and synthesis techniques with applications in automated design of integrated circuits

In this dissertation, tree optimization and synthesis algorithms are studied in the context of automated design of integrated circuits. It is shown how these techniques can be employed in interconnect optimization, synthesis and buffering while considering the following issues: routing and buffer blockages, minimization of interconnect and buffer costs, congestion, exploitation of temporal locality among the sinks and addressing sink polarity requirements. A universal tree synthesis algorithm (U-Tree) is presented and it is demonstrated how to implement other algorithms (P-Tree, S-Tree, SP-Tree) using this flow. Then a set of techniques for placement-coupled, timing-driven logic replication is presented. Two components are at the core of the approach. First is an algorithm for optimal timing-driven fanin tree embedding derived from the U-Tree framework. The algorithm is very general in that it can easily incorporate complex objective functions (e.g., placement costs) and can perform embedding on any graph-based target. Second we introduce the Replication Tree which allows us to induce large fanin trees from a given circuit which can then be optimized by the embedder. We have built an optimization engine around these two ideas and report promising results for the FPGA domain.