A methodology for the verification of a “system on chip”

Proceedings of the 36th annual ACM/IEEE Design Automation Conference(1999)

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摘要
1.ABSTRACT This paper summarizes the verification effort of a complex ASIC designated to be an "all in one" ISDN network router. This ASIC is unique because it actually consists of many independent compo-nents, called "cores" (including the processor). The integration of these components onto one chip results in an ISOC (Integrated System On a Chip). The complexity of verifying an ISOC is virtually impossible without a proper methodology. This paper presents the methodology developed for veri-fying the router. In particular, the verification method as well as the tools that were built to execute this method are presented. Finally, a summary of the verification results is given.
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关键词
verification,test and debugging,systems on chip,fabrication,debugging,chip scale packaging,protocols,system testing,system on chip,isdn,chip,system on a chip,integrable system,application specific integrated circuits,silicon,formal verification,hardware
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