Sidewinder - A Scalable Ilp-Based Router

We propose Sidewinder, a new global router that combines pattern routing and maze routing in a novel, incremental, ILP formulation. It is the first flat ILP-based approach scalable enough to consider over 10(4) GCells at once. Moreover, it also can be used as a component in previously proposed multi-level and progressive ILP schemes. Sidewinder is particularly good at finding routes with minimal via count, which can improve yield in sub-90nm technologies. Other innovations in our work include an ILP construction based on a dynamically-updated congestion map and the use of C-shape routes to alleviate local congestion and improve routability. On well-known benchmarks, Sidewinder improves routed wirelength and reduces via count by over 6% compared to ILP-based BoxRouter 1.0 and 35.8% compared to DLM-based FCR 1.0. This easy-to-implement methodology is extensible to detail routing of ASICs as well as FPGAs where it can account for complex design rules and models.