A unified approach to hardware verification through a heterogeneous logic of design diagrams

Abstract: Designers use a variety of notations, some of them diagrammatic, while developing systems. Unfortunately,verification tools mainly support single, textual logics. This gap between design practiceand verification methodology makes formal verification difficult for designers to apply. Properly formalized,however, diagrams are just as suitable for formal proof as conventional textual notations.Furthermore, heterogeneous logics, those with multiple syntactic representations, support formal...