Whitespace-aware TSV arrangement in 3D clock tree synthesis

ISVLSI, pp. 115-120, 2013.

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Keywords:
clock tree synthesis3d icswhitespace-aware tsv arrangementtrees (mathematics)deferred-merge embeddingMore(19+)
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The algorithm consists of three stages: sink pre-clustering, TWA-3D-method of means and medians topology generation, and deferred-merge embedding merging segment reconstruction

Abstract:

Through-silicon via (TSV) could provide vertical connections between different dies in three-dimensional integrated circuits (3D ICs), but the significant silicon area occupied by TSVs may bring great challenge to designers in 3D clock tree synthesis (CTS) because only few whitespace blocks can be used for clock TSVs after floorplan and p...More

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Introduction
  • As CMOS process technology continuously scaling down, through-silicon-via (TSV) based three-dimensional integrated circuits (3D ICs) have drawn much more attention recently.
  • TSVs are usually placed in the whitespace among macro blocks or cells, a bad arrangement of TSVs may incur longer wirelength since the available TSV might be far away from its connected cells.
  • Intellectual Property (IP) and Standard cell based design has been extensively used to reduce design cost, but after floorplan and placement, only few whitespace blocks are reserved for clock TSVs [3].
Highlights
  • As CMOS process technology continuously scaling down, through-silicon-via (TSV) based three-dimensional integrated circuits (3D ICs) have drawn much more attention recently
  • In the TWA-3D-method of means and medians (MMM) clock tree topology generation stage, we extend the 3D-MMM method by judging whether the current x/y-cut between multiple dies is appropriate, considering whitespace to ensure that each sink set contains whitespace
  • Different from the existing 3D design, which focused on slew-aware buffer insertion during the bottom-up embedding procedure of deferred-merge embedding (DME) [5, 11, 12], our slew-aware buffering is performed after clock routing for the following reasons: 1) it is easy to achieve with an O(n) time complexity; 2) the buffer delay may change under different supply voltage, so exact zero skew numerical buffer solution during bottom-up embedding procedure of DME under one supply voltage may change under another
  • The algorithm consists of three stages: sink pre-clustering, TWA-3D-MMM topology generation, and DME merging segment reconstruction
  • We propose a whitespace-aware 3D clock tree synthesis (CTS) flow
  • Experiment results show that our method is more practical and efficient, compared to the traditional 3D-MMM based one with TSV moving adjustment
Results
  • After exhaustively sweeping the TSV bound from 1 to 50 the authors observe that in Fig. 9, as the TSV bound increase little by little, the 3D-MMM-DBM solutions suffer from severe power and skew problems, while the method shows consistent good results
  • This is not difficult to imagine because a larger TSV bound means more TSV moving adjustment, which may worsen clock latency unbalance.
  • The authors will consider more cases such like multiple dies, uneven sink distribution, and explore the dependency of the whitespace and #TSV with the power reduction in the future work
Conclusion
  • The authors formulate the whitespace-aware TSV arrangement problem in 3D CTS and propose a practical and efficient algorithm to deal with it.
  • The algorithm consists of three stages: sink pre-clustering, TWA-3D-MMM topology generation, and DME merging segment reconstruction.
  • The authors propose a whitespace-aware 3D CTS flow.
  • Experiment results show that the method is more practical and efficient, compared to the traditional 3D-MMM based one with TSV moving adjustment
Summary
  • Introduction:

    As CMOS process technology continuously scaling down, through-silicon-via (TSV) based three-dimensional integrated circuits (3D ICs) have drawn much more attention recently.
  • TSVs are usually placed in the whitespace among macro blocks or cells, a bad arrangement of TSVs may incur longer wirelength since the available TSV might be far away from its connected cells.
  • Intellectual Property (IP) and Standard cell based design has been extensively used to reduce design cost, but after floorplan and placement, only few whitespace blocks are reserved for clock TSVs [3].
  • Results:

    After exhaustively sweeping the TSV bound from 1 to 50 the authors observe that in Fig. 9, as the TSV bound increase little by little, the 3D-MMM-DBM solutions suffer from severe power and skew problems, while the method shows consistent good results
  • This is not difficult to imagine because a larger TSV bound means more TSV moving adjustment, which may worsen clock latency unbalance.
  • The authors will consider more cases such like multiple dies, uneven sink distribution, and explore the dependency of the whitespace and #TSV with the power reduction in the future work
  • Conclusion:

    The authors formulate the whitespace-aware TSV arrangement problem in 3D CTS and propose a practical and efficient algorithm to deal with it.
  • The algorithm consists of three stages: sink pre-clustering, TWA-3D-MMM topology generation, and DME merging segment reconstruction.
  • The authors propose a whitespace-aware 3D CTS flow.
  • Experiment results show that the method is more practical and efficient, compared to the traditional 3D-MMM based one with TSV moving adjustment
Tables
  • Table1: IMPACT OF DIFFERENT WHITESPACE AREA ON #TSV, SKEW, POWER AND SLEW BETWEEN 3D-MMM-DBM METHOD AND OUR PROPOSED METHOD (TSV BOUND IS SET TO BE 20, #BLOCK AND #TSV MEANS THE NUMBER OF WHITESPACE BLOCKS AND TSVS, VIO MEANS SLEW VIOLATION)
  • Table2: IMPACT OF DIFFERENT TSV BOUND ON DIFFERENT BENCHMARKS BETWEEN 3D-MMM-DBM AND OUR METHOD
Download tables as Excel
Funding
  • This work was supported by National Science and Technology Major Project (2010ZX01030-001-001-04, 2011ZX01035-001-001-002), National Natural Science Foundation of China (No 61261160501, 61028006, 61076035), and Tsinghua University Initiative Scientific Research Program
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