Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2014）
摘要
Through silicon via (TSV) is a widely used interconnect technology in 3-D integrated circuits. This paper shows that defective TSVs can induce small delay faults in surrounding logic gates. We present simulation results of TSV-induced small delay fault (TSDF) because of mechanical stress or pinhole leakage. A test technique is proposed to detect TSDF using a physical-aware fault extractor and timing-aware automatic test pattern generation. This technique requires no DfT area overhead and no direct TSV probing. Experimental results on benchmark circuits show that test coverage can be improved by 22% and 10% for stress-induced and leakage-induced TSDF, respectively. In our results, the test length overheads of both TSDFs are ${
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关键词
integrated circuit testing,mechanical stress,benchmark circuits,small delay fault (sdf),stress-induced tsdf,test technique,through silicon via (tvs),tsv-induced small delay faults,three-dimensional integrated circuits,automatic test pattern generation,through silicon via,3d integrated circuits,fault diagnosis,leakage-induced tsdf,mechanical stress and pinhole leakage,physical-aware fault extractor,interconnect technology,defective tsv,timing-aware automatic test pattern generation,logic gates,pinhole leakage
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