A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
ISSCC（2010）
摘要
7 Gb/s/pin operation without bank group restriction in a GDDR5 SDRAM is achieved by skewed control logic and current-mode I/O sense amplifiers with regular calibration from replica impedance monitors. The bank-to-bank active time is shortened to 2.5 ns by a FIFO-based BLSA enabler, 2.0 ns latency VPP generator and active jitter canceler. The chip is fabricated in a 50 nm DRAM process in a 61.6 mm2 die area.
更多查看译文
关键词
calibration,time 2.5 ns,time 2 ns,vpp generator,fifo-based blsa enabler,amplifiers,jitter,no bank-group restriction,gddr5 sdram,skewed control logic,dram chips,regular calibration,current-mode i/o sense amplifiers,active jitter canceler,size 50 nm,replica impedance monitors,bank-to-bank active time,current-mode circuits,generators
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要