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We developed a flexible FPGA architectural evaluation framework fpgaEVA-LP for detailed power consumption evaluation of a wide range of look-up tables-based FPGA architectures in 0.10um technology
Architecture evaluation for power-efficient FPGAs
FPGA, pp.175-184, (2003)
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs; (ii) We develop a tool that ...More
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- Power has become a significant design constraint due to the demand of battery-powered devices in the rapid growth of personal wireless communications and other portable digital applications.
- Recently, [Poon02] presented a flexible FPGA power model associated with architecture parameters and evaluated different FPGA architectures for power efficiency.
- Several issues such as glitch power analysis and switching activity calculation considering spatial and temporal signal correlations were not addressed thoroughly.
- Experimental results in an old technology (0.35um) are not very useful in predicting the trend of future FPGA designs
- Power has become a significant design constraint due to the demand of battery-powered devices in the rapid growth of personal wireless communications and other portable digital applications
- Many FPGA architecture evaluations have been performed using the metric of area and performance, there is limited work published about FPGA architecture evaluations for power efficiency. [Kusse98] used a Xilinx XC4003A FPGA test board to carry out power dissipation measurement and reported a power breakdown of various FPGA components. [Shang02] analyzed the dynamic power consumption for Xilinx Virtex-II FPGA family. [Weiß00] presented the power consumption for Xilinx Virtex architecture using their emulation environment
- A variety of logic block architectures defined by the different architecture parameters such as look-up tables size and cluster size are examined for their power efficiency and performance
- We implemented a mixed-level FPGA power estimation model that combines both switch-level modeling for interconnects and SPICE pre-characterization based modeling for logic blocks and look-up tables
- A switching activity calculator based on real-delay model was implemented and was able to capture glitch power
- The leakage power can be up to 59% of the total power on average for certain architectures
- We developed a flexible FPGA architectural evaluation framework fpgaEVA-LP for detailed power consumption evaluation of a wide range of look-up tables-based FPGA architectures in 0.10um technology
- The authors present the experimental results obtained by the evaluation framework fpgaEVA-LP.
- A variety of logic block architectures defined by the different architecture parameters such as LUT size and cluster size are examined for their power efficiency and performance.
- Three different routing architectures are investigated.
- Routing_default, the default architecture in Circuit.
- Logic optimization (SIS) Map to k -input LUTs (RASP) Mapped netlist Arch.
- Timing-driven packing (T-VPACK), placement and routing (VPR).
- Wmin Routing with W = 1.2 Wmin (VPR) VPRBCG.
- Delay/capacitance extraction and back -annotation BC - netlist Power estimation
- The authors implemented a mixed-level FPGA power estimation model that combines both switch-level modeling for interconnects and SPICE pre-characterization based modeling for logic blocks and LUTs. The authors generated gate-level netlists with back-annotated capacitances and delays extracted from local and global interconnects after placement and routing.
- A switching activity calculator based on real-delay model was implemented and was able to capture glitch power.
- This work identified the future research directions for power reduction.
- The authors' future work is to study leakage efficient FPGA circuits and architectures
- Table1: Key delay numbers for paths in Figure 5 (k=4)
- Table2: Mixed-level Power Model (N.A.: Not applicable)
- Table3: Dynamic Power of a 4-LUT under different input vector pairs
- Table4: Logic Block and Routing Architectures
- Table5: Average Transition Density per Circuit Node
- Table6: Glitch Power
- This work is partially supported by NSF Grant CCR-0096383, NSF CAREER Award CCR-0093273, and SRC grant 2002HJ1008
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