Reducing cache and TLB power by exploiting memory region and privilege level semantics.
Journal of Systems Architecture（2013）
The L1 cache in today’s high-performance processors accesses all ways of a selected set in parallel. This constitutes a major source of energy inefficiency: at most one of the N fetched blocks can be useful in an N-way set-associative cache. The other N-1 cachelines will all be tag mismatches and subsequently discarded.更多
First-level cache,Translation lookaside buffer,Memory regions,Ring level,Simulation