Binary-Level Hardware/Software Partitioning of MediaBench, NetBench, and EEMBC Benchmarks

msra

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摘要
Hardware/software partitioning can greatly reduce execution time and energy consumption of embedded systems. However, traditional source-level partitioning approaches have had limited success due in part to tool flow problems. Previous research introduced binary-level hardware/software partitioning as a solution to the tool flow problem, showing competitive speedups at the cost of almost double the hardware area. We incorporate powerful automated decompilation methods, previously developed by other researchers for binary translation tools, into a binary partitioning tool. Such incorporation eliminates the area overhead of previous approaches. Furthermore, we apply our tool to much larger examples than previous binary partitioning efforts, using examples from MediaBench, NetBench, and EEMBC benchmarks, and we show that speedups are still comparable with source-level partitioning even on these larger examples. Our results show that binary partitioning can result in average speedups of 3.0 and energy savings of 52% over software-only implementations, using an architecture similar to commercially available single-chip microprocessor/configurable-logic platforms.
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关键词
platform,low power,hardware/software partitioning,codesign,decompilation,binary translation.,synthesis,fpga,speedup
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