Post-Placement Functional Decomposition for FPGAs

This work explores the effect of adding a simple functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has com- pleted, alternative decompositions of the logic on the critical path are examined for potential delay improvements. The placed circuit is then modified to use the best decomposi- tions found. Any placement illegalities introduced by the new decompositions are resolved by an incremental place- ment step. Experiments conducted on Altera's Stratix chips indicate that this functional decomposition technique can provide a performance improvement of 7.6% on average, and up to 26.3% on a set of industrial designs.