Clock gating architectures for FPGA power reduction

Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock signal on registers whose outputs do not affect cir- cuit outputs. We consider and evaluate FPGA clock network architectures with built-in clock gating capability and de- scribe a flexible placement algorithm that can operate with various gating granularities (various sizes of device regions containing clock loads that can be gated together). Results show thatdependingon the clock gatingarchitecture and the fraction of time clock signals are enabled, clock power can be reduced by over 50%, and results suggest that a fine gran- ularity gating architecture yields significant power benefits.