A study of tighter lower bounds in LP relaxation based placement.

Qingzhou (Ben) Wang,Devang Jariwala,John Lillis

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI(2005)

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摘要
Placement strategies for cell-based designs which use a linear programming (LP) relaxation are widely believed to have certain weaknesses. Among these is the phenomenon that the relaxed placement produced by the LP-solver often has excessive cell overlap; this makes the relaxed solution quite distant from a legal one and raises questions about the value of the relaxed solution. An implication of this phenomenon is that, while the objective function value (HPWL) yielded by the LP is a valid lower bound on the achievable wire-length, it is quite distant from known upper bounds produced by quality placement tools - i.e., the lower bounds appear to be loose. In this paper we experiment with some straightforward generalizations of the basic LP-formulation aimed at tightening the lower bound. We show that this approach has an interesting dual effect: in addition to tightening lower bounds, it also results in a quantifiably better cell distribution than the simpler LP-formulation. Based on this idea, we have developed a placer which employs the Relaxation Based Local Search framework. Experimental results are reported for PEKO and MCNC FPGA benchmarks.
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