Improving Memory System Performance for Soft Vector Processors

Recently proposed vector processing extensions (9, 10) can significantly improve the performance of a conventional FPGA-based soft processor, but significantly increase the pressure on the memory system to keep pace. In this work we investigate methods of improving the memory system for soft vector processors via (i) tuning the data cache config- uration, namely its depth and line size, and (ii) hardware prefetching mechanisms. We evaluate on our VESPA soft vector processor connected to DDR and executing hand- vectorized benchmarks from the EEMBC industry-standard benchmark suite. We find that cache configuration provides a significant area/performance trade-off for designers to wield, providing near 2x average performance for 1.8x the system area. We also demonstrate that proper prefetching can improve performance by 28% on average, and up to 2.2x in the best case.