A chip-level electrostatic discharge simulation strategy
ICCAD, pp. 315-318, 2004.
o padnetwork reduction algorithmelectrostatic discharge simulationchip-level simulationsimulation methodMore(11+)
This work presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node VDD net and 1000 I...More
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