SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power
ASP-DAC（2011）
摘要
Field programmable gate arrays (FPGAs) are widely used in VLSI applications due to their flexibility to implement logical functions, fast total turn-around time and low none-recurring engineering cost. SRAM-based FPGAs are the most popular FPGAs in the market. However, as process technologies advance to nanometer-scale regime, the issue of reliability of devices becomes critical. Soft errors are increasingly becoming a reliability concern because of the shrinking process dimensions. In this paper we study the technology mapping problem for FPGA circuits to reduce the occurrence of soft errors under the chip performance constraint and power reduction. Compared to two power-optimization mapping algorithms, SVmap [17] and Emap [15] respectively, we reduce the soft error rate by 40.6% with a 2.22% power overhead and 48.0% with a 2.18% power overhead using 6-LUTs.
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关键词
power optimization mapping algorithm,power-optimization mapping algorithm,power overhead,soft error tolerant mapping,popular fpgas,fault tolerant computing,sram chips,reliability concern,soft error tolerant mapping algorithm,fpga design,fpga circuit,process dimension,sram-based fpga design,low power,setmap,soft error rate,technology mapping problem,chip performance constraint,field programmable gate arrays,process technology,power reduction,soft error,sram-based fpgas,cost function,field programmable gate array,logic gate,logic gates,functional equation,power optimization,switches,chip
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