Area efficient layouts of the Batcher sorting networks Part of this work was done at Bell-Labs, Lucent Technologies, while the author was on leave from the Technion

NETWORKS(2001)

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摘要
In the early 1980s, the grid area required by the sorting nets of Batcher for input vectors of length N was investigated by Thompson. He showed that the Omega (N-2) area was necessary and sufficient, but the hidden constant factors, both for the lower and upper bounds, were not discussed. In this paper, a lower bound of (N - 1)(2)/2 is proven, for the area required by any sorting network. Upper bounds of 4N(2) and 3N(2) are shown for the bitonic sorter and the odd-even sorter, respectively. In the layouts, which are presented to establish these upper bounds, slanted lines are used and there are no knock-knees. (C) 2001 John Wiley & Sons, Inc.
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关键词
sorting networks,Batcher,bitonic,odd-even,grid area,VLSI,ATM switch,bounds
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