Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2013)
摘要
Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing need for domain-specific acceleration technologies, this paper describes a design methodology (i) to automatically generate a domain-specific coarse-grained array from a set of representative applications and (ii) to introduce limited forms of architectural generality to increase the likelihood that additional applications can be successfully mapped onto it. In particular, coarse-grained arrays generated using our approach are intended to be integrated into customizable processors that use application-specific instruction set extensions to accelerate performance and reduce energy; rather than implementing these extensions using application-specific integrated circuit (ASIC) logic, which lacks flexibility, they can be synthesized onto our reconfigurable array instead, allowing the processor to be used for a variety of applications in related domains. Results show that our array is around $2\times$ slower and $15\times$ larger than an ultimately efficient ASIC implementation, and thus far more efficient than field-programmable gate arrays (FPGAs), which are known to be 3–4$\times$ slower and 20–40$\times$ larger. Additionally, we estimate that our array is usually around $2\times$ larger and $2\times$ slower than an accelerator synthesized using traditional datapath merging, which has, if any, very limited flexibility beyond the design set of DFGs.
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关键词
application specific integrated circuits,data flow graphs,field programmable gate arrays,instruction sets,logic design,reconfigurable architectures,ASIC logic,DFG,FPGA,application specific instruction set extensions,application specific integrated circuit,coarse-grained array,data flow graphs,datapath merging,domain-specific acceleration technology,domain-specific reconfigurable arrays,field programmable gate arrays,hardware acceleration,selective flexibility,Datapaths,FPGA routing,domain-specific customization,flexibility,reconfigurable arrays
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