Power minimization methodology for VCTL topologies.

Osman Kubilay Ekekon,Samed Maltabas,Martin Margala,Ugur Çilingiroglu

SoCC（2010）

引用 3|浏览4

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CMOS integrated circuits,adders,capacitance,logic design,logic gates,threshold logic,AND-OR gates,CMOS technology,NMOS capacitance,PMOS capacitance,VCTL topology,full adder,power minimization methodology,size 65 nm,varicap threshold logic,voltage 0.8 V

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