A Variant of a Radix-10 Combinational Multiplier
2008 IEEE International Symposium on Circuits and Systems (ISCAS)（2008）
Key words
CMOS logic circuits,adders,combinational circuits,digital arithmetic,multiplying circuits,CMOS technology,binary form,combinational decimal multiplier,decimal carry-save adders,multi-operand decimal addition,partial product array,radix-10 combinational multiplier,size 90 nm,time 2.51 ns,time 2.65 ns
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