Bitline contacts in high density SRAMs: design for testability and stressability

ITC, pp. 776-782, 2001.

Cited by: 7|Views18


Process scaling and the need for smaller SRAM cellschallenges process technologies to make millions of robustand reliable bitline contacts on a single chip. Anotherchallenge is to identify marginal, resistive and unreliablebitline contacts given the inherent electrical characteristicsof the SRAM cell. This paper describes two designtechni...More



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