Bitline contacts in high density SRAMs: design for testability and stressability

Process scaling and the need for smaller SRAM cellschallenges process technologies to make millions of robustand reliable bitline contacts on a single chip. Anotherchallenge is to identify marginal, resistive and unreliablebitline contacts given the inherent electrical characteristicsof the SRAM cell. This paper describes two designtechniques that improve the screenability and stressabilityof bitline contacts in high-density SRAMs. Thesetechniques are developed to overcome the lack ofdetectability of resistive bitline contacts in SRAM cells.