Mesh-Structured On-Chip Power/Ground: Design for Minimum Inductance and Characterization for Fast R, L Extraction
custom integrated circuits conference（1999）
摘要
For high-speed circuits, on-chip inductance can no longer be ignored. This paper deals with inductance in the pres- ence of multi-layered meshes used for on-chip power supplies. We have shown ways of designing power/ground (p/g) mesh that reduce inductance. Accurate 3-dimensional inductance extrac- tion problem is intractable for large chips. We have demon- strated the feasibility of using flexible-accuracy empirical formulae for fast determination of inductance. We have reported results obtained from a real chip.
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关键词
VLSI,circuit layout CAD,circuit simulation,inductance,integrated circuit interconnections,integrated circuit layout,integrated circuit modelling,power integrated circuits,3D inductance extraction problem,fast RL extraction,flexible-accuracy empirical formulae,high-speed circuits,mesh-structured on-chip power/ground,minimum inductance,multilayered meshes,on-chip inductance,on-chip power supplies,skin effect
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