Physical synthesis techniques for fpga optimization

In the deep sub-micron era, the interconnect delay becomes the dominating part of the critical path. The variability of the long interconnect wire significantly affects the high performance designs. Physical synthesis emerges as a major tool to resolve the timing closure problem. Our research takes the advantages of modern FPGA architectures, and proposes three strategies to battle the emerging long interconnect delays. The first strategy is a "preemptive strike." The strike reduces the long inter-cluster delays before any placement is committed. Our simultaneous mapping and clustering algorithm proposes a dynamic programming scheme, which is the first work that achieves optimal delay under the general delay model. The second strategy is to conduct back and force "battles" on the synthesis and physical design border. A placement step is performed to discover the long interconnect delay. Then an iterative approach is carried out to find the optimal mapping solution based on the placement assumption. Heuristics, such as the area overflow consideration, are exploited in the algorithm. The third strategy is to use "precision-guided bombs" to target the "bad" wires. Our SPFD global rewiring scheme and feasibility theorem enhance the existing rewiring algorithm. They fully utilize the logic flexibility of the FPGA device, and increase the potential to replace the long interconnect wires.