A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation

Kwisung Yoo,Dongmyung Lee,Gunhee Han,Sung Min Park,Won-Seok Oh

ISSCC（2007）

引用 5|浏览11

暂无评分

摘要

A 2.5Gb/s limiting amplifier is realized in a standard 0.18μm CMOS process, exploiting the negative-impedance compensation technique. Measurements show 2.5Gb/s operation (0.5pF ESD protection diodes included) with 40dB gain, 21psrms jitter for 231-1 PRBS, 9.5mVpp input sensitivity with BER <10-12, and 5.2mW power dissipation from a 1.2V supply. The chip core occupies 0.25×0.1mm2.

查看译文

关键词

cmos integrated circuits,limiting amplifier,2.5 gbit/s,5.2 mw,amplifiers,cmos technology,optical communication equipment,1.2 v,negative-impedance compensation,40 db,0.18 micron,power dissipation,chip

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要