The Limits Of Digital Testing For Dynamic Circuits

Dynamic circuits are faster and have a different circuit topology from their static counterparts. These topological differences require changes in fault modeling and rest strategies. Digital resting, while adequate for static logic, misses numerous faults in dynamic circuits due to the implicit assumptions surrounding The stuck-at fault model. A fault model reduction technique was employed which simplifies large circuits without loss of information on the ways that circuits can fail. Numerous faults were singly inserted and possible faulty operation was analyzed. The faults missed by digital testing are detailed and alternative test strategies are discussed. In many cases significant dynamic circuit robustness is lost due to faults which are digitally undetectable.