Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.
GLSVLSI(2011)
摘要
ABSTRACTThis paper presents a novel way to analyze the variation of analog circuits taking layout-dependent variation parameters into consideration. Focusing on 90nm process, we reveal Monte Carlo simulation based on independent parameters Vth and ² collected from the test chip can not account for the measurement results of fabricated op-amp circuits with different layouts styles. In the comparison of the simulation and the measurement results, we clarify the impacts by the parasitics of wires and STI stress as well as the correlation of the variation of Vth and ². Besides, we also propose an efficient approach of Monte Carlo simulation converting all variation parameters to the channel widths of MOSFETs.
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