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Active leakage power optimization for FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, no. 3 (2006): 423-437

Cited by: 204|Views104
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Abstract

We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-...More

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