Active leakage power optimization for FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 423-437, 2004.
CMOS logic circuitscircuit CADcircuit optimisationfield programmable gate arraysintegrated circuit designMore(19+)
We consider active leakage power dissipation in FPGAs and present a "no cost" approach for active leakage reduction. It is well-known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. Our leakage reduction technique leverages a fundamental property of basic FPGA logic elements (look-up-...More
Best Paper of FPGA, 2004