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A fully pipelined memoryless 17.8 Gbps AES-128 encryptor

FPGA, pp.207-215, (2003)

Cited by: 201|Views118
EI

Abstract

A fully pipelined implementation of the Advanced Encryption Standard encryption algorithm with 128-bit input and key length (AES-128) was implemented on Xilinx' Virtex-E and Virtex-II devices. The design is called SIG-AES-E and it implements the S-boxes combinatorially and thus requires no internal memory. It is concluded, that SIG-AES-E ...More

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