High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives
IEEE Transactions on Very Large Scale Integration Systems（2014）
摘要
This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 mm2.
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关键词
solid-state drives,optimisation,cmos process,vlsi.,high data rate,operating frequency,high-throughput architecture,hardware complexity,data sequence,bch codes,size 130 nm,serial interface standards,massive-parallel decoder,bch code,flash memory channel,digital integrated circuits (ics),low-complexity bch decoding architecture,flash memory,optimizing methods,encoder,nand flash memory applications,vlsi,decoding throughput,cmos digital integrated circuits,circuit optimization,decoding,flash memories
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