Fracturable FPGA Logic Elements

The longstanding conventional wisdom in FPGA architecture is that a 4-input lookup-table (LUT) provides the most efficient tradeoff between area and delay. This paper introduces a new adaptive logic module based on fracturable 6- LUTs with the goal of fundamentally altering this relationship. This logic module can achieve the performance benefits of larger LUT sizes (up to 7) while actually decreasing area cost through sharing of input muxing resources and additional features that allow multiple functions to share the same LUT-mask. Benchmarking results show a 15% performance improvement and 12% area decrease using a 6,2 ALM comparing to a standard 4-LUT based logic module on the same process technology and routing architecture.