Connecting different worlds: technology abstraction for reliability-aware design and test
DATE(2014)
摘要
The rapid shrinking of device geometries in the nanometer regime requires new technology-aware design methodologies. These must be able to evaluate the resilience of the circuit throughout all System on Chip (SoC) abstraction levels. To successfully guide design decisions at the system level, reliability models, which abstract technology information, are required to identify those parts of the system where additional protection in the form of hardware or software countermeasures is most effective. Interfaces such as the presented Resilience Articulation Point (RAP) or the Reliability Interchange Information Format (RIIF) are required to enable EDA-assisted analysis and propagation of reliability information. The models are discussed from different perspectives, such as design and test.
更多查看译文
关键词
integrated circuit design,integrated circuit reliability,integrated circuit testing,system-on-chip,EDA assisted analysis,reliability aware design,reliability aware test,reliability interchange information format,resilience articulation point,system on chip abstraction levels,technology abstraction,technology aware design methodologies
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络