The Effect of Logic Block Complexity on Area of Programmable Gate Arrays

This paper explores the tradeoff between the area of a Programmable Gate Array (PGA) and the functionality of its logic block. A set of industrial circuits are implemented as PGAs using tools for technology mapping, placement and routing. A simple model allows the exploration of a range of programming technologies, and accounts for the area required by wiring. Experiments indicate that for combinational logic blocks implemented using lookup tables, the best number of inputs to use is between three and four, and that a D flip-flop should always be included in the logic block. These results are independent of the programming technology. Introduction The Programmable Gate Array is an exciting new idea in semi-custom integrated circuits that reduces the IC manufacturing time from months to minutes and prototype cost from tens of kilodollars to under $100. The PGA was introduced in (Cart86) and newer versions have been presented in (Hsie87,Hsie88,ElGa88,ElAy88). It is similar to a gate array in structure, but can be field-programmedto specify the function of the basic logic blocks and their interconnection. The architecture of a PGA consists of its logic block function, interconnection scheme, and I/O block design. In this paper we focus on the logic block design, and study the effect of logic block complexity on PGA area. We ignore speed considerations, even though they are very important, because we need first to determine the plausible architectures from an area perspective. The architectural choices that affect the area of a PGA depend on the programming technology, which is the underlying method by which the logic function is configuredand connections are made. For example, the programming technology used in (Hsie88) creates logic functions using static RAM lookup tables, and performs routing using pass transistors and multiplexors. The PGA described in (ElGa88) uses an anti-fuse for both logic and interconnection that, when blown, causes two metal tracks to be electri- cally joined. The logic block design is an important factor in the PGA architecture. If it has insufficient functionality then too much area must be devoted to the interconnection. If the block has excess functionality then it may suffer from under-utilization and wasted active area. We address two questions concerning the logic block design: First, should the basic logic block contain a D flip-flop? Our experiments indicate that the presence of a D flip-flop in the logic block is always desirable, regardless of the programming technology. Second, if the logic block contains an arbitrary K to 1 combinational function, what is the best number (K) of inputs to use? Our results show that the best number of inputs remains nearly constant over a wide range of programming technologies and was almost the same whether or not the block contained a D flip-flop. Experimental Procedure To answer these questions, our approach is to implement a set of circuits in a variety of logic blocks and programming technologies, and determine the area required for each.