A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

Oleksiy Tyshchenko,Ali Sheikholeslami,Hirotaka Tamura,Masaya Kibune,Hisakatsu Yamaguchi,Junji Ogawa

J. Solid-State Circuits（2010）

引用 40|浏览10

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摘要

This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully confirmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies 0.51 mm(2) and consumes 178.4 mW at 5 Gb/s.

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关键词

CMOS digital integrated circuits,analogue-digital conversion,clock and data recovery circuits,ADC-based feedforward CDR,CMOS,bit rate 5 Gbit/s,clock and data recovery,power 178.4 mW,size 65 nm,zero crossings,ADC-based CDR,CDR,Clock and data recovery,all-digital CDR,blind-sampling CDR,feed-forward CDR

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