A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems

Zongjian Chen,Priya Ananthanarayanan, Sukalp Biswas,Brian Campbell,Hao Chen,Shaishav Desai,Dominic Go,Rajat Goel,Vincent von Kaenel, Jason Kassoff,Fabian Klass,Weichun Ku,Tony Li,Jonathon Lin, Khurram Malik,Anup Mehta,Daniel Murray,Eric Shiu,Chris Shuler,Sribalan Santhanam, Greg Scott,Junji Sugisawa,Toshinari Takayanagi, Honkai John Tarn,Pradeep Trivedi,James Wang,Ricky Wen,John Yong

ISSCC（2007）

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摘要

An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed

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关键词

integrated memory circuits,integrated memory subsystems,coherent crossbar interconnect,cache storage,low-power electronics,2 mbytes,2 ghz,system-on-chip,65 nm,25 w,logic design,l2 cache,integrated circuit design,dual power cores,i/o subsystems,low-power design techniques,system performance,chip,low power electronics,system on chip

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