Sub-30-nm Complementary Metal–Oxide–Semiconductor Field-Effect Transistor with Pt-Incorporated Fully Ni-Silicide/SiON Gate Stack

We demonstrated an ideal scaling of inversion gate dielectric thickness (T-inv) without the decrease in the channel strain of a short-channel planar transistor using a Pt-incorporated fully Ni-silicide (Ni-FUSI)/SiON gate stack. We have achieved drive currents of 1.1/0.65 mA/mu m at an off-leakage current of 50 nA/mu m for the sub-30-nm n- and p-metal-oxide-semiconductor field effect transistors (MOSFETs). Because the decrease in gate length was larger than the T-inv scaling while maintaining a high drive current, the Ni-FUSI/SiON gate stack improved the intrinsic delay of the scaled inverter. (C) 2010 The Japan Society of Applied Physics